International Journal of Advanced Research in Computer and Communication Engineering

A monthly peer-reviewed online and print journal

ISSN Online 2278-1021
ISSN Print 2319-5940

Since 2012

Abstract: Multipliers are main building block of ALU, which improves the speed of many functions like Fourier transformation, digital filters and Digital Signal Processor (DSP).  For any function we need to reduce the delay in system. Vedic mathematics provides mathematical approaches to increased speed and reduced power consumption as in comparison to conventional multiplier designs. Vedic multiplication algorithm with Vedic mathematics Urdhava Tiryakbhyam Sutra (UTS) method and Carry Select Adder (CSA) technique are useful to reduce power. UTM means vertically and cross wise vedic mathematics. It is ancient Indian technique used for decimal number multiplications. The speed of the computation process is increased and the processing time is reduced due to decrease of combinational path delay compared to the existing multipliers. Leakage power and low speed has become a general issue in circuit design. In our proposed multiplication algorithm, we get less time delay compared to other algorithms. In this paper, Low Power Vedic Architecture is designed reviewed. These Vedic multiplier architectures are decrease in the power consumption and generate the results faster.

Keywords: VLSI, CSA, Vedic Multiplier, RCL, High Speed, Urdhava Tiryakbhyam Sutra


PDF | DOI: 10.17148/IJARCCE.2019.81008