Abstract: In modern computing systems, fast and efficient arithmetic operations are essential for enhancing overall performance. The Carry Look-Ahead Adder (CLA) is widely used due to its reduced propagation delay compared to conventional ripple-carry adders. However, further optimization is required to improve speed, power efficiency, and circuit complexity. This paper presents a novel design of an optimized CLA using hybrid logic, integrating CMOS technology with a custom-designed memristor model implemented in LTSpice XVII. The proposed approach leverages the low-power characteristics of memristors while maintaining the robustness and switching reliability of CMOS technology. By utilizing Voltage-Controlled Resistors (VCRs) as memristive elements, the design achieves significant reductions in propagation delay and power consumption.Extensive simulations and performance evaluations demonstrate the superiority of the proposed CLA in terms of speed and energy efficiency compared to conventional CLAs. The results indicate that hybrid CMOS-memristor logic can be a promising approach for designing next-generation arithmetic circuits. This study provides valuable insights into the practical implementation of hybrid logic circuits and establishes a foundation for future research in memristor-based arithmetic units.
Keywords: Memrisor, CLA, LTSpice XVII, Hybrid Logic
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DOI:
10.17148/IJARCCE.2025.14379
