Abstract: Over the years, the focus of IC Enterprises hasn’t shifted from optimizing various performance parameters to validate Moore’s law. These enterprises are still striving to scale down these parameters. However, near 20 nm range challenges posed regarding the strength, various side-effects hampering the functionality of the IC. With an aim to bring out a solution this research has been done. The outcome assessing parameters are decreased power dissipation and delay in an Array multiplier implemented using FINFET instead of MOSFET. Tool used is HSPICE of synopsis. Simulation is done and comparison drawn between FINFET and MOSFET implementation for 32nm technology. The outcome validates the advantage of FINFET over MOS.
Keywords: FinFET, Average Power, Multiplier
| DOI: 10.17148/IJARCCE.2020.9213