πŸ“ž +91-7667918914 | βœ‰οΈ ijarcce@gmail.com
International Journal of Advanced Research in Computer and Communication Engineering
International Journal of Advanced Research in Computer and Communication Engineering A monthly Peer-reviewed & Refereed journal
ISSN Online 2278-1021ISSN Print 2319-5940Since 2012
IJARCCE adheres to the suggestive parameters outlined by the University Grants Commission (UGC) for peer-reviewed journals, upholding high standards of research quality, ethical publishing, and academic excellence.
← Back to VOLUME 3, ISSUE 2, FEBRUARY 2014

Adaptive Power Reduction Technique for Adder using Multi Bit Flip Flop

T.M.MINIPRIYA, M.RAMYA, T.MOHANAPRIYA, S.THILAGAVATHI, P.C.FRANKLIN PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai, India Assistant Professor, Electronics and Communication Engineering Dept., S.A Engineering College, Chennai, India PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai, India PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai, India PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai,

πŸ‘ 33 views
Downloads:PDF Download PDF
Creative Commons License This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite:

[1] T.M.MINIPRIYA, M.RAMYA, T.MOHANAPRIYA, S.THILAGAVATHI, P.C.FRANKLIN PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai, India Assistant Professor, Electronics and Communication Engineering Dept., S.A Engineering College, Chennai, India PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai, India PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai, India PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai, , β€œAdaptive Power Reduction Technique for Adder using Multi Bit Flip Flop,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)

Share this Paper