Abstract: In Nanometer regime, process variation and circuit aging cause remarkable and unnecessary and ambiguous circuit system characteristics and the resultant effects on the system design remains a great challenge to the designers. Even though the Guard band design can provide a little protection against these effects yet creates an increased design issues. Hence there is a strong need to equip circuits with the capability of tuning themselves and thereby compensating the variations with a proposed adaptive nature. This work is an effort towards supply voltage adaptation for variation resilience in VLSI interconnects. The main idea is a boostable repeater design that can transiently and autonomously raise its internal voltage rail to boost switching speed. The boosting can be turned on/off to compensate variations. The boostable repeater design achieves fine-grained voltage adaptation without stand-alone voltage regulators or an additional power grid. Since interconnect is a widely recognized cause of bottleneck in chip performance, and tremendous repeaters are employed on chip designs, boostable repeater has plenty of chances to improve system robustness.

Keywords: Interconnects, Process variations, switching time.


Downloads: PDF | DOI: 10.17148/IJARCCE.2022.111203

How to Cite:

[1] Manjula Jayamma, Y. Mallikarjuna Rao, Rama Subbaiah Boya, N. Ramanjaneyulu, "Performance Analysis of Repeater Insertion Technique for Future VLSI Interconnects," International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2022.111203

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