Abstract: An adder is used to physically realise addition, which is a fundamental operation in microprocessing and digital signal processing technology. Two common high-speed, low-power adder architectures are the carry-lookahead adder (CLA) and the carry-select adder (CSLA). Using a hybrid CLA architecture, which substitutes a small-size ripple-carry adder (RCA) for a sub-CLA at the least significant bit positions, can increase the speed performance of a CLA architecture. On the other hand, by using binary-to-excess-1 code (BEC) converters, the power dissipation of a CSLA using full adders and 2:1 multiplexers can be decreased. Many CLAs and CSLAs have separate designs that have been discussed in the literature. A direct comparison of their results based on the design metrics would be helpful. To enable a comparison, we constructed 32-bit accurate and approximate additions in homogeneous and hybrid CLAs, as well as CSLAs with and without the BEC converters. We looked at a 32/28 nm complementary metal-oxide semiconductor (CMOS) process with a typical-case process-voltage-temperature (PVT) specification for the gate-level implementations. The findings indicate that, in terms of speed and power, the hybrid CLA/RCA architecture is preferable to the CLA and CSLA structures for performing precise and approximative additions.
KeyWords: arithmetic circuits; ripple-carry adder; carry-lookahead adder; carry-select adder; digital
design; standard cells; CMOS
|
DOI:
10.17148/IJARCCE.2023.12449
