Abstract: As the world is moving on the FinFET technology sizes is scaling down accordingly which will benefit the logic devices as the cost for the customers will be reduced and also the area required for placing it also reduces. FinFET technologies provides significant performance boosts for both logic as well as RF/mmWave over planar technologies. FinFET technology is used in 5G technologies where we need to consider the RF performance such as mobility improvement. The path of RF technology development is to concentrate on how to detach the manufacturing of RF devices from the scaling of logic devices with the least amount of negative influence on the coexistence of RF and logic devices. In order to get technology in right aspect, we need to develop runsets to check if layers are perfectly placed without any error before manufacturing it. DRC (Design Rule Check) is an important part for checking the BEOL (Backend-Of-The-Line) configuration. By maximising design productivity and acting as a doorway to the foundry where the integrated circuit (IC) will be manufactured, a well-made physical design kit (PDK) can help an integrated circuit (IC) designer achieve that goal.The main outcome of this work is to develop a runset which will provide an error free circuit design which will be beneficial for RF and the logic devices.
Keywords: DRC, Via, 5G Technology. FinFET.
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DOI:
10.17148/IJARCCE.2022.11673
