Abstract: Due to the ongoing reduction in chip size, power minimization is the primary design focus in VLSI circuits. The development of VLSI systems relies heavily on CMOS technology because it uses less power. Modern integrated circuit (IC) designers aim to create digital circuits with low power consumption in very large scale integration (VLSI) ICs. This is done to increase the circuit's battery life, especially if it is intended for wearable technology. Counters are frequently employed in digital circuits, and these counters demand a lot of power. Reduced power usage across the board is necessary to have an effective digital system. Thus, this paper aims to provide the various power optimization techniques that can be incorporated in Johnson Counter design in order to reduce the power dissipation of the counter. Also these techniques can be incorporated in other counter design as well.
Keywords: Complementary Metal Oxide Semiconductor (CMOS), Integrated Circuit (IC), Very Large Scale Integration (VLSI), Low power, Johnson Counter, Flip-Flop.
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DOI:
10.17148/IJARCCE.2023.12460
