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International Journal of Advanced Research in Computer and Communication Engineering A monthly Peer-reviewed & Refereed journal
ISSN Online 2278-1021ISSN Print 2319-5940Since 2012
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← Back to VOLUME 12, ISSUE 7, JULY 2023

Study of stacked high-k Gate-All-Around FET

Thatholu Hari Sai Kumar, Ellapu Yagna Varahala Rao, Jeevan Rao Batakala

DOI: 10.17148/IJARCCE.2023.12703

Abstract: In this paper, the characteristics of Gate-All-Around Field Effect Transistor (GAA FET) with stack high-k are studied by using the Silvaco Atlas simulations. By using of high dielectric constant material in the place of gate oxide reduces the leakage current and improve the Short Channels Effects (SCEs) like Drain Induced Barrier Lowering (DIBL) and Subthreshold Swing (SS). Gate dielectric material of HfO2 along with SiO2 are used to analyze various electrical characteristics at 22nm GAA FET. The analysis included the ON current, threshold voltage, DIBL, SS, leakage current at 22nm gate length.  Keywords: Dielectric material, subthreshold slope, DIBL

How to Cite:

[1] Thatholu Hari Sai Kumar, Ellapu Yagna Varahala Rao, Jeevan Rao Batakala, “Study of stacked high-k Gate-All-Around FET,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2023.12703